ABSTRACT
This work provides an analysis of a set of approximate full adder
circuits in 16nm CMOS device technology, with the goal of identifying
how these designs behave in a specific environment and
applying voltage scaling when compared to conventional exact
adders, focusing on reduction in power consumption. The results
allow designers to evaluate the pros and cons of each design in error
tolerant applications, especially in comparison with exact adders.
In nominal tension, there was reduction of up to 90% in power consumption
in XNOR based inexact FAs, and up to 75% gain in power
and 25% gain in delay with CMOS simplifications. In near-threshold
voltages, it was possible to obtain up to 22% improvement in delay
and 50% in power consumption, when comparing the same designs
operating under nominal voltage. The best results were obtained
when applying voltage reduction in approximate designs, which
reached improvements in power of up to 98%.