Abstract
Currently, most computers adopt the System-on-Chip (SoC) approach,
integrating various components into a single chip. Traditionally,
the interconnection of these components is achieved
through buses, which are essential for effective communication.
However, as system complexity and performance demands increase,
Networks-on-Chip (NoCs) have emerged as a more efficient alternative,
offering greater scalability and bandwidth. The integration
of SoC components with buses or NoCs remains a challenge, requiring
specific adaptations that make the process labor-intensive
and prone to errors. This work aims to simplify this integration
by developing a graphical interface tool that automates the integration
of AXI bus-based components into the XINA NoC. The
tool, developed in Python with a Qt interface, was validated using
traffic generators and monitors and integrated into the AMD/Xilinx
Vivado development environment.