Modern high-performance systems increasingly face memory latency as a dominant bottleneck, even when running on CPUs with substantial computational capacity. This work investigates how software-level design choices—particularly data layout and concurrency control—directly influence cache efficiency and overall CPU utilization in transactional workloads. We implement a simplified, in-memory clone of the Brazilian Pix instant-payment system in Rust and compare a naïve, lock-bound architecture with an optimized, memory-aware version. Using hardware performance counters collected with perf, we show that applying techniques such as lock sharding, data-oriented struct redesign, and zero-copy mutation reduces the L1 data-cache miss rate from 43.6% to 6.7% and increases IPC by 33% (from 0.48 to 0.64). These results demonstrate that aligning software structure with processor memory hierarchies can shift a workload from latency-bound to compute-bound behavior, yielding substantial throughput gains without changes to hardware. The study highlights the importance of cache-conscious programming in real-time financial systems and provides a reproducible methodology for evaluating memory-centric optimizations in modern multicore environments.