The H.266 Versatile Video Coding (VVC) standard introduces a set of mandatory pre-processing smoothing filters applied to reference samples prior to angular intra prediction. Although these filters lie on the critical path of the prediction process and directly affect latency and hardware complexity, existing VVC hardware designs either omit their implementation or assume pre-filtered samples. This work presents the first dedicated hardware architecture for the VVC reference sample smoothing filter at the decoder side, supporting all block sizes from 8x8 to 64x64. A bit-level reformulation of the 3-tap FIR filter enables an optimized datapath that reduces arithmetic complexity, eliminating unnecessary computations while preserving compliance with the specification. Synthesized on an Intel Cyclone V FPGA, the design occupies only 595 ALMs and 553 registers (1% of the device) and achieves a maximum frequency of 181.79 MHz. Throughput analysis shows that real-time operation is sustained for 8K video at 60 fps with a clock requirement of only 31.10 MHz, enabling underclocking and power reduction. The results demonstrate that the proposed architecture provides a small, high-throughput, and fully compliant solution suitable for integration into a complete VVC decoder